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Prof. Dr. Veit Dominik Kunz (MBA)

Fakultät Life Sciences
Department Verfahrenstechnik
Elektrotechnik / Erneuerbare Energien
Ulmenliet 20
21033 Hamburg
Raum N 5.03
T +49.40.428 75-6378
veitdominik.kunz(@)haw-hamburg.de
Sprechzeiten: Während der VL-Zeit im SoSe2019 ab 21.03: donnerstags von ~13:30 bis 14:30

Ämter/Gremien

Prüfungsausschussvorsitzender VT

Lehrgebiete/Lehrfächer

- Advanced Electrical Engineering

- Elektrische Energietechnik

- Elektronik 1

- Elektrotechnik 1

- Informatik 1

- Physik 2

- Power Electronics & Grids

- Project Management

Forschungsprojekte/-gebiete

FLEDERWIND

Publikationen

• “Change of Paradigm: Product Development in High-Tech Organisations Before and After the Technology Feasibility Point”, V.D.Kunz, L.Warren, 19th International Product Development Management Conference, June 2012, Manchester, UK
• “A Comprehensive Energy Management System for Domestic Applications”, T.Rudolph, V.D.Kunz, S.Börger, 26th European Photovoltaic Solar Energy Conference and Exhibition, September 2011, Hamburg, Germany
• “From Innovation to Market Entry: A Strategic Management Model for Emerging Technologies”, V.D.Kunz, L.Warren, 2011, Vol. 23, No.4, Technology Analysis and Strategic Management
• “Asymmetric Gate-Induced Drain Leakage and Body Leakage in Vertical MOSFETs with reduced parasitic capacitance”, E.Gili, D.Kunz, T.Uchino, M.M.A.Hakim, C.H.de Groot, T.Uchino, S.Hall, P.Ashburn, Vol. 53, No. 5, May 2006, IEEE Transactions on Electron Devices
• “Reduced Size High Voltage Output Drivers for Smart Power Applications”, V.D.Kunz, P.Gassot, www.analogzone.com/technotes, April 2005
• “CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance”, V.D.Kunz, C.H.de Groot, E.Gili, T.Uchino, S.Hall, P.Ashburn, ESSDERC 2004, Leuven, Belgium
• “Recent developments in deca-nanometer vertical MOSFETs”, S.Hall, D.C.Donaghy, O.Buiu, E.Gili, T.Uchino, V.D.Kunz, C.H.de Groot, P.Ashburn, Vol. 72, 2004, Microelectronic Engineering
• “Single, Double and Surround Gate Vertical MOSFETs with Reduced Parasitic Capacitance”, E.Gili, V.D.Kunz, C.H.de Groot, T.Uchino, P.Ashburn, D.C.Donaghy, S.Hall, Y.Wang, P.L.F.Hemment, Vol.48, 2004, Solid-State Electronics
• “Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket”, D.Donaghy, S.Hall, C.H.de Groot, V.D.Kunz, P.Ashburn, Vol.51, No.1, January 2004, IEEE Transactions on Electron Devices
• “Electrical Characteristics of Single, Double & Surround Gate Vertical MOSFETs with Reduced Overlap Capacitance”, E.Gili, V.D.Kunz, C.H.de Groot, T.Uchino, D.C.Donaghy, S.Hall, P.Ashburn, ESSDERC 2003, Estoril, Portugal
• “Recent developments in deca-nanometer vertical MOSFETs”, D.Donaghy, S.Hall, O.Buiu, E.Gili, T.Uchino, V.D.Kunz, C.H.de Groot, P.Ashburn, Proceedings of Insulating Films on Semiconductors Conference, 2003, Barcelona, Spain
• “Polycrystalline silicon-germanium emitters for gain control with application to SiGe HBTs”, V.D.Kunz, C.H.de Groot, S.Hall, P.Ashburn, Vol. 50, No. 6, June 2003, IEEE Transactions on Electron Devices
• “Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation”, V.D.Kunz, T.Uchino, C.H.de Groot, P.Ashburn, D.C.Donaghy, S.Hall, Y.Wang, P.L.F.Hemment, Vol. 50, No. 6, June 2003, IEEE Transactions on Electron Devices
• “Reduction of parasitic capacitance in vertical MOSFETs by fillet local oxidation (FILOX)”, C.H.de Groot, V.D. Kunz, T.Uchino, P.Ashburn, D.C.Donaghy, S.Hall, Y.Wang, P.L.F.Hemment, ULIS 2003, Udine, Italy
• “Modelling of gain control in SiGe HBTs and Si bipolar transistors by Ge incorporation in the polysilicon emitter”, V.D.Kunz, C.H.de Groot, I.M.Anteney, A.I.Abdul-Rahim, S.Hall, P.Ashburn, Nanotech 2003, San Francisco
• “Ion implanted vertical MOSFETs”, C.H.de Groot, V.D.Kunz, P.Ashburn, D.C.Donaghy, S.Hall, Proceedings of Nano and Giga challenges in Microelectronics research, 2002, Moscow
• “Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors”, V.D.Kunz, C.H.de Groot, S.Hall, I.M.Anteney, A.I.Abdul-Rahim, P.Ashburn, ESSDERC 2002, Florence, Italy
• “Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket, in a circuit environment”, D.Donaghy, S.Hall, V.D.Kunz, C.H.de Groot, P.Ashburn, ESSDERC 2002, Florence, Italy
• “Thermal Evaluation of a micromachined PCR chip”, C.G.J.Schabmueller, A.G.R.Evans, G.Ensell, A.Brunschweiler, H.Sehr, T.E.G.Niblock, V.D.Kunz, M.Bu, Micromechanics Europe 2002, Sinaia, Romania
• “A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket”, A.C.Lamb, L.S.Riley, S.Hall, V.D.Kunz, C.H.de Groot, P.Ashburn, ESSDERC 2001, Nürnberg, Germany

Letzte Änderung: 16.04.13

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